1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor (MOS) transistor and fabricating method thereof. More particularly, the present invention relates to a high voltage MOS transistor and fabricating method thereof.
2. Description of the Related Art
High voltage metal-oxide-semiconductor (MOS) transistors are widely used in electronic products that require high voltage, such as flash memory or the control circuit of a flat panel display. Since the high voltage MOS transistor must operate at a high voltage without any signs of electrical breakdown, the breakdown voltage of a high voltage MOS transistor is higher than most conventional devices.
FIG. 1 is a top view of a conventional high voltage metal-oxide-semiconductor (MOS) transistor. As shown in FIG. 1, the high voltage MOS transistor 100 mainly comprises a substrate 100, a well 110, two drift regions 120a/120b, two source/drain regions 140a/140b, a channel region 130, a gate 150 and a gate insulation layer (not shown). The well 110 is formed within the substrate 100. The two drift regions 120a/120b are formed within the well 110. The source/drain regions 140a/140b are formed within the drift regions 120a/120b, respectively. The channel region 130 is formed between the source region 140a and the drain region 140b. The gate 150 is formed over the substrate 100 and the gate insulation layer is formed between the gate 150 and the substrate 100. In general, the width of the device is determined by the width W4 of the source region 140a and the drain region 140b. In FIG. 1, the width W1 of the gate 150 in the high voltage device is greater than the width W2 of the drift regions 120a/120b as well as the width W3 of the channel region 130. One major disadvantage for this layout is that when the width of the device is smaller, charges in the source region 140a can easily flow from the drift region 120a along the edge of the gate 150 into the drift region 120b, leading to unnecessary current leakage.
FIG. 2 is a top view of another conventional high voltage metal-oxide-semiconductor (MOS) transistor. Compared with FIG. 1, the width W3′ of the channel region 230 of the high voltage MOS transistor in FIG. 2 is reduced. In other words, the width W3′ of the channel region 230 is smaller than the width W2 of the drift regions 120a/120b. However, one major problem for this layout is that the sub-threshold current will increase following a reduced dimension of the device.